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| 16 Mbit (x8) Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 SST39VF1681 / 16822.7V 16Mb (x8) MPF+ memories Preliminary Specifications FEATURES: * Organized as 2M x8 * Single Voltage Read and Write Operations - 2.7-3.6V * Superior Reliability - Endurance: 100,000 Cycles (Typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 5 MHz) - Active Current: 9 mA (typical) - Standby Current: 3 A (typical) - Auto Low Power Mode: 3 A (typical) * Hardware Block-Protection/WP# Input Pin - Top Block-Protection (top 64 KByte) for SST39VF1682 - Bottom Block-Protection (bottom 64 KByte) for SST39VF1681 * Sector-Erase Capability - Uniform 4 KByte sectors * Block-Erase Capability - Uniform 64 KByte blocks * Chip-Erase Capability * Erase-Suspend/Erase-Resume Capabilities * Hardware Reset Pin (RST#) * Security-ID Feature - SST: 128 bits; User: 128 bits * Fast Read Access Time: - 70 ns - 90 ns * Latched Address and Data * Fast Erase and Byte-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 40 ms (typical) - Byte-Program Time: 7 s (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bits - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and Command sets * Packages Available - 48-ball TFBGA (6mm x 8mm) - 48-lead TSOP (12mm x 20mm) PRODUCT DESCRIPTION The SST39VF168x devices are 2M x8 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF168x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39VF168x devices provide a typical Byte-Program time of 7 sec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF168x devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 1 they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF168x are offered in both 48-ball TFBGA and 48-lead TSOP packages. See Figures 1 and 2 for pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39VF168x also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 3 A. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF168x offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms and Figure 23 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector(Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. Read The Read operation of the SST39VF168x is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Byte-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Byte-Program Operation The SST39VF168x are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the ByteProgram operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 s. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 2 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Chip-Erase Operation The SST39VF168x provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 9 for timing diagram, and Figure 23 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low. `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 20 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 7 for Toggle Bit timing diagram and Figure 20 for a flowchart. TABLE 1: WRITE OPERATION STATUS Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read from Erase Suspended Sector/Block Read from Non- Erase Suspended Sector/Block Program Write Operation Status Detection The SST39VF168x provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. DQ7 DQ7# 0 1 DQ6 Toggle Toggle 1 DQ2 No Toggle Toggle Toggle Data Data Data DQ7# Toggle N/A T1.0 1243 Data# Polling (DQ7) When the SST39VF168x are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a (c)2003 Silicon Storage Technology, Inc. Note: DQ7 and DQ2 require a valid address when reading status information. S71243-03-000 11/03 3 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Data Protection The SST39VF168x provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 15). The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39VF168x provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. Hardware Block Protection The SST39VF1682 supports top hardware block protection, which protects the top 64 KByte block of the device. The SST39VF1681 supports bottom hardware block protection, which protects the bottom 64 KByte block of the device. The Boot Block address ranges are described in Table 2. Program and Erase operations are prevented on the 64 KByte when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. TABLE 2: BOOT BLOCK ADDRESS RANGES Product Bottom Boot Block SST39VF1681 Top Boot Block SST39VF1682 1F0000H-1FFFFFH T2.1 1243 Address Range 000000H-00FFFFH Common Flash Memory Interface (CFI) The SST39VF168x also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address AAAH in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 4 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Product Identification The Product Identification mode identifies the devices as the SST39VF1681 and SST39VF1682, and manufacturer as SST. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 11 for the software ID Entry and Read timing diagram, and Figure 21 for the software ID Entry command sequence flowchart. TABLE 3: PRODUCT IDENTIFICATION Address Manufacturer's ID Device ID SST39VF1681 SST39VF1682 0001H 0001H C8H C9H T3.1 1243 apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 13 for timing waveform, and Figures 21 and 22 for flowcharts. Security ID The SST39VF168x devices offer a 256-bit Security ID space which is divided into two 128-bit segments. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Byte-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Security ID space can be queried by executing a three-byte command sequence with Enter-Sec-ID command (88H) at address AAAH in the last byte sequence. Execute the Exit-Sec-ID command to exit this mode. Refer to Table 6 for more details. Data BFH 0000H Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that FUNCTIONAL BLOCK DIAGRAM X-Decoder SuperFlash Memory Memory Address Address Buffer & Latches Y-Decoder CE# OE# WE# WP# RESET# I/O Buffers and Data Latches Control Logic DQ7 - DQ0 1243 B1.0 (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 5 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications TOP VIEW (balls facing down) 6 5 4 3 2 1 A14 A13 A15 A10 A9 A11 NC A16 A17 NC A12 DQ7 NC A20 DQ5 NC NC DQ2 NC A6 A2 DQ0 NC A0 VSS NC DQ6 VDD DQ4 NC DQ3 NC DQ1 1243 48-tfbga B3K P1.0 WE# RST# NC WP# A19 A8 A4 A18 A5 A7 A3 A1 CE# OE# VSS A B C D E F G H FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TFBGA A16 A15 A14 A13 A12 A11 A10 A9 A20 NC WE# RST# NC WP# NC A19 A18 A8 A7 A6 A5 A4 A3 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1243 48-tsop P2.0 A17 NC VSS A0 DQ7 NC DQ6 NC DQ5 NC DQ4 VDD NC DQ3 NC DQ2 NC DQ1 NC DQ0 OE# VSS CE# A1 FIGURE 2: PIN ASSIGNMENTS FOR 48-LEAD TSOP (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 6 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications TABLE 4: PIN DESCRIPTION Symbol AMS1-A0 Pin Name Address Inputs Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To protect the top/bottom boot block from Erase/Program operation when grounded. To reset and return the device to Read mode. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 2.7-3.6V Unconnected pins. T4.1 1243 DQ7-DQ0 Data Input/output WP# RST# CE# OE# WE# VDD VSS NC Write Protect Reset Chip Enable Output Enable Write Enable Power Supply Ground No Connection 1. AMS = Most significant address AMS = A20 for SST39VF1681/1682 TABLE 5: OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 6 T5.0 1243 CE# VIL VIL VIL VIH X X OE# VIL VIH VIH X VIL X WE# VIH VIL VIL X X VIH DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT Address AIN AIN Sector or block address, XXH for Chip-Erase X X X 1. X can be VIL or VIH, but no other value. (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 7 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications TABLE 6: SOFTWARE COMMAND SEQUENCE Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID4 1st Bus Write Cycle Addr1 AAAH AAAH AAAH AAAH XXXXH XXXXH AAAH AAAH AAAH AAAH AAAH AAAH XXH Data AAH AAH AAH AAH B0H 30H AAH AAH AAH AAH AAH AAH F0H 2nd Bus Write Cycle Addr1 555H 555H 555H 555H Data 55H 55H 55H 55H 3rd Bus Write Cycle Addr1 AAAH AAAH AAAH AAAH Data A0H 80H 80H 80H 4th Bus Write Cycle Addr1 BA2 AAAH AAAH AAAH Data Data AAH AAH AAH 5th Bus Write Cycle Addr1 555H 555H 555H Data 55H 55H 55H 6th Bus Write Cycle Addr1 SAX3 BAX3 AAAH Data 50H 30H 10H 555H 555H 555H 555H 555H 555H 55H 55H 55H 55H 55H 55H AAAH AAAH AAAH AAAH AAAH AAAH 88H A5H 85H 90H 98H F0H BA5 XXH5 Data 00H User Security ID Byte-Program User Security ID Program Lock-Out Software ID Entry6,7 CFI Query Entry Software ID Exit8,9 /CFI Exit/Sec ID Exit Software ID Exit8,9 /CFI Exit/Sec ID Exit T6.1 1243 1. Address format A11-A0 (Hex). Addresses A20-A12 can be VIL or VIH, but no other value, for Command sequence for SST39VF1681/1682. 2. BA = Program Byte Address 3. SAX for Sector-Erase; uses AMS-A12 address lines BAX, for Block-Erase; uses AMS-A16 address lines AMS = Most significant address AMS = A20 for SST39VF1681/1682 4. With AMS-A5 = 0; Sec ID is read with A4-A0, SST ID is read with A4 = 0 (Address range = 00000H to 0000FH), User ID is read with A4 = 1 (Address range = 00010H to 0001FH). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 5. Valid Byte Addresses for Sec ID are from 000000H-00000FH and 000020H-00002FH. 6. The device does not remain in Software Product ID Mode if powered down. 7. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST39VF1681 Device ID = C8H, is read with A0 = 1, SST39VF1682 Device ID = C9H, is read with A0 = 1, AMS = Most significant address AMS = A20 for SST39VF1681/1682 8. Both Software ID Exit operations are equivalent 9. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed "0" bits cannot be reversed to "1"). (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 8 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications TABLE 7: CFI QUERY IDENTIFICATION STRING1 Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 51H 52H 59H 01H 07H 00H 00H 00H 00H 00H 00H Data Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T7.1 1243 1. Refer to CFI publication 100 for more details. TABLE 8: SYSTEM INTERFACE INFORMATION Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 27H 36H 00H 00H 03H 00H 04H 05H 01H 00H 01H 01H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min. (00H = no VPP pin) VPP max. (00H = no VPP pin) Typical time out for Byte-Program 2N s (23 = 8 s) Typical time out for min. size buffer program 2N s (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (25 = 32 ms) Maximum time out for Byte-Program 2N times typical (21 x 23 = 16 s) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) T8.1 1243 TABLE 9: DEVICE GEOMETRY INFORMATION Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 15H 00H 00H 00H 00H 02H FFH 01H 10H 00H 1FH 00H 00H 01H Data Device size = 2N Bytes (15H = 21; 221 = 2 MByte) Flash Device Interface description; 00H = x8-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 511 + 1 = 512 sectors (01FF = 511 z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (1F = 31) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T9.1 1243 (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 9 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C OF VDD 2.7-3.6V 2.7-3.6V AC CONDITIONS TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 17 and 18 (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 10 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications TABLE 10: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1 Limits Symbol IDD Parameter Power Supply Current Read3 Program and Erase ISB IALP ILI ILIW ILO VIL VILC VIH VIHC VOL VOH Standby VDD Current Auto Low Power Input Leakage Current Input Leakage Current on WP# pin and RST# Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 0.2 18 35 20 20 1 10 10 0.8 0.3 mA mA A A A A A V V V V V V Min Max Units Test Conditions Address input=VILT/VIHT2, at f=5 MHz, VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD Max CE#=VILC, VDD=VDD Max All inputs=VSS or VDD, WE#=VIHC VIN=GND to VDD, VDD=VDD Max WP#=GND to VDD or RST#=GND to VDD VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min T10.8 1243 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VDD = 3V. Not 100% tested. 2. See Figure 17 3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V. TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ1 TPU-WRITE 1 Parameter Power-up to Read Operation Power-up to Program/Erase Operation Minimum 100 100 Units s s T11.0 1243 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: CAPACITANCE Parameter CI/O1 CIN 1 (Ta = 25C, f=1 Mhz, other pins open) Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 12 pF 6 pF T12.0 1243 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: RELIABILITY CHARACTERISTICS Symbol NEND TDR1 ILTH 1 1,2 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T13.2 1243 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications AC CHARACTERISTICS TABLE 14: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V SST39VF168x-70 Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR 1 SST39VF168x-90 Min 90 Max 90 90 45 0 0 Units ns ns ns ns ns ns 30 30 0 500 50 ns ns ns ns ns 20 s T14.1 1243 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change RST# Pulse Width RST# High before Read RST# Pin Low to Read Mode Min 70 Max 70 70 35 0 0 20 20 0 500 50 20 TRY1,2 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations. TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH1 TDS TDH1 TIDA1 TSE TBE TSCE Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase 0 30 0 0 0 10 40 40 30 30 30 0 150 25 25 50 Min Max 10 Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms T15.0 1243 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 12 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications TRC ADDRESS AMS-0 TAA CE# TCE OE# VIH WE# TOLZ TOE TOHZ TCHZ HIGH-Z DATA VALID 1243 F02.0 DQ15-0 HIGH-Z TCLZ TOH DATA VALID Note: AMS = Most Significant Address AMS = A20 for SST39VF168x FIGURE 3: READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 AAA TAH TWP WE# TAS OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 1243 F03.0 555 AAA ADDR TDH TWPH TDS Note: AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 13 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 AAA TAH TCP CE# TAS OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 1243 F04.0 555 AAA ADDR TDH TCPH TDS Note: AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES DQ7 DATA DATA# DATA# DATA 1243 F05.0 Note: AMS = Most Significant Address AMS = A20 for SST39VF168x FIGURE 6: DATA# POLLING TIMING DIAGRAM (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 14 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 1243 F06.0 Note: AMS = Most Significant Address AMS = A20 for SST39VF168x FIGURE 7: TOGGLE BITS TIMING DIAGRAM SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 AAA 555 AAA AAA 555 AAA TSCE CE# OE# TWP WE# DQ7-0 AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 10 SW5 1243 F07.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.) AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 15 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 AAA 555 AAA AAA 555 BAX TBE CE# OE# TWP WE# DQ7-0 AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 30 SW5 1243 F08.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.) BAX = Block Address AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 16 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 AAA 555 AAA AAA 555 SAX TSE CE# OE# TWP WE# DQ7-0 AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 50 SW5 1243 F9.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.) SAX = Sector Address AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 17 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS AMS-0 AAA 555 AAA 0000 0001 CE# OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 TAA BF Device ID 1243 F10.1 TIDA Note: Device ID - See Table 3 on page 5 AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 11: SOFTWARE ID ENTRY AND READ THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS AMS-0 AAA 555 AAA CE# OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 98 SW2 1243 F11.1 TIDA TAA Note: AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 12: CFI QUERY ENTRY AND READ (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 18 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS AMS-0 AAA 555 AAA DQ7-0 AA 55 F0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 Note: AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. 1243 F12.1 FIGURE 13: SOFTWARE ID EXIT/CFI EXIT THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS AMS-0 AAA 555 AAA CE# OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 88 SW2 TAA 1243 F13.0 TIDA Note: AMS = Most Significant Address AMS = A20 for SST39VF168x WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 14: SEC ID ENTRY (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 19 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications TRP RST# CE#/OE# TRHR 1243 F14.0 FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS) TRP RST# TRY CE#/OE# End-of-Write Detection (Toggle-Bit) 1243 F15.0 FIGURE 16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION) (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 20 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1243 F16.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1243 F17.0 FIGURE 18: A TEST LOAD EXAMPLE (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 21 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Start Load data: AAH Address: AAAH Load data: 55H Address: 555H Load data: A0H Address: AAAH Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1243 F18.0 X can be VIL or VIH, but no other value FIGURE 19: BYTE-PROGRAM ALGORITHM (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 22 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Internal Timer Program/Erase Initiated Toggle Bit Program/Erase Initiated Data# Polling Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Program/Erase Completed Read same word No Is DQ7 = true data? Yes No Does DQ6 match? Yes Program/Erase Completed Program/Erase Completed 1243 F19.0 FIGURE 20: WAIT OPTIONS (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 23 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications CFI Query Entry Command Sequence Load data: AAH Address: AAAH Sec ID Query Entry Command Sequence Load data: AAH Address: AAAH Software Product ID Entry Command Sequence Load data: AAH Address: AAAH Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 98H Address: AAAH Load data: 88H Address: AAAH Load data: 90H Address: 5555H Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Sec ID Read Software ID X can be VIL or VIH, but no other value 1243 F20.0 FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 24 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Software ID Exit/CFI Exit/Sec ID Exit Command Sequence Load data: AAH Address: AAAH Load data: F0H Address: XXH Load data: 55H Address: 555H Wait TIDA Load data: F0H Address: AAAH Return to normal operation Wait TIDA Return to normal operation X can be VIL or VIH, but no other value 1243 F21.0 FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 25 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications Chip-Erase Command Sequence Load data: AAH Address: AAAH Sector-Erase Command Sequence Load data: AAH Address: AAAH Block-Erase Command Sequence Load data: AAH Address: AAAH Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 80H Address: AAAH Load data: 80H Address: AAAH Load data: 80H Address: AAAH Load data: AAH Address: AAAH Load data: AAH Address: AAAH Load data: AAH Address: AAAH Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 10H Address: AAAH Load data: 50H Address: SAX Load data: 30H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1243 F22.0 X can be VIL or VIH, but no other value FIGURE 23: ERASE COMMAND SEQUENCE (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 26 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications PRODUCT ORDERING INFORMATION SST 39 XX VF 1681 XX XXXX - 70 - XXX 4C XX - B3K - XXX E X Environmental Attribute E = non-Pb Package Modifier K = 48 leads Package Type B3 = TFBGA (6mm x 8mm, 0.8mm pitch) E = TSOP (type1, die up, 12mm x 20mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Hardware Block Protection 1 = Bottom Boot-Block 2 = Top Boot-Block Device Density 168 = 16 Mbit Voltage V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash Valid Combinations for SST39VF1681 SST39VF1681-70-4C-EK SST39VF1681-70-4C-EKE SST39VF1681-70-4I-EK SST39VF1681-70-4I-EKE SST39VF1681-90-4I-EK SST39VF1681-90-4I-EKE SST39VF1681-70-4C-B3K SST39VF1681-70-4C-B3KE SST39VF1681-70-4I-B3K SST39VF1681-70-4I-B3KE Valid Combinations for SST39VF1682 SST39VF1682-70-4C-EK SST39VF1682-70-4C-EKE SST39VF1682-70-4I-EK SST39VF1682-70-4I-EKE SST39VF1682-90-4I-EK SST39VF1682-90-4I-EKE SST39VF1682-70-4C-B3K SST39VF1682-70-4C-B3KE SST39VF1682-70-4I-B3K SST39VF1682-70-4I-B3KE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 27 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier 0.50 BSC 12.20 11.80 0.27 0.17 18.50 18.30 0.15 0.05 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50 1mm 48-tsop-EK-8 48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM SST PACKAGE CODE: EK X 20MM (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 28 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 Preliminary Specifications TOP VIEW 8.00 0.20 BOTTOM VIEW 5.60 0.80 0.45 0.05 (48X) 6 5 4 3 2 1 0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20 6 5 4 3 2 1 SIDE VIEW 1.10 0.10 A1 CORNER SEATING PLANE 0.35 0.05 0.12 1mm Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-4 48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM SST PACKAGE CODE: B3K X 8MM TABLE 16: REVISION HISTORY Number 00 01 02 03 Description Date May 2003 Sep 2003 Oct 2003 Nov 2003 * * * * * * Initial release Change product number from 166x to 168x Added B3K package and associated MPNs (See page 27) Removed 90 ns Commercial temperature for the EK and EKE packages 2004 Data Book Updated B3K package diagram Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2003 Silicon Storage Technology, Inc. S71243-03-000 11/03 29 |
Price & Availability of SST39VF1681
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